FIG. 1 shows a QAM receiver according to the prior art.
As shown in FIG. 1, the QAM receiver receives an analog signal from a transmitter S. The data signal coming from a data source is transmitted by the transmitter S to a tuner T via a transmission channel. The tuner T precedes the actual QAM receiver IC and is used for tuning to the received signal. The received signal is delivered by the tuner T via an anti-aliasing filter AAF to at least one analog/digital converter ADC. The ADC output signal is supplied to a mixing stage. The in-phase signal component I and the quadrature component Q are present at the output of the mixing stage. The in-phase signal I and the quadrature phase signal Q are multiplied by a control signal in the time domain. The output signals of the mixing stage are supplied to digital resampling filters. The resampling filters perform a resampling of the received signal which, at the same time, is subjected to band limiting. During this process, the resampling filters receive a control signal from a numerically controlled oscillator NCO within a clock phase loop. The control signal sets the time of the sampling in dependence on a filtered clock phase error signal TP.
At the output end, the resampling filters RES are connected to an automatic gain control AGC. The automatic gain control AGC is followed by so-called matched filters MF. During transmission via the real transmission channel, the received signal, as a rule, exhibits linear distortion and an additional noise component. The QAM receiver has the task of reconstructing the bit sequence of the data source from the received signal. The matched filters (MF) are digital receive filters which are matched to a transmit filter in the transmitter S, in such a manner that the amplitude of the received signal is maximum at the sampling times. The matched filter MF can be adaptively constructed so that it can be adapted to the transmission channel. Before or after the matched filters (MF), an adaptive equalizer can be additionally provided which compensates for the distortion of the transmission channel.
The output signal of the matched filters (MF) is fed back to the automatic gain control AGC in a feedback loop. In addition, the output signals of the two matched filters MF are supplied to a clock phase detector TPD and a carrier frequency detector TFD. The clock phase detector TPD generates from the two output signals a clock phase error detection signal TP which is supplied to a downstream digital filter B. The clock phase error detection signal TP specifies the deviation of the clock phase of the received signal from a nominal value.
The filtered clock phase error detection signal TP is supplied to the numerically controlled oscillator NCOB which generates a control signal for setting the sampling times of the resampling filters RES.
The carrier frequency detector TFD forms from the output signals of the two matched filters MF a carrier frequency error detection signal TF which is supplied to a digital filter A. The filtered carrier frequency error detection signal TF is supplied to a numerically controlled oscillator NCOA which generates a control signal for the mixing stage.
The mixing stage forms a carrier frequency loop with the resampling filters RES, the gain control AGC, the matched filters MF, the carrier frequency detector TFD, the filter A and the numerically controlled oscillator NCOA.
The resampling filters RES form a clock phase loop with the automatic gain control AGC, the two matched filters MF, the clock phase detector TPD, the filter B and the numerically controlled oscillator NCOB.
The QAM receiver of the prior art, shown in FIG. 1, is thus constructed with two stages. The carrier frequency loop effects control in a first carrier frequency capture range until the carrier frequency error detection signal TF exhibits the error value zero at a nominal carrier frequency. In the second stage, the clock phase loop effects control until the clock phase error detection signal TP also exhibits the value zero within a clock phase capture range. This is indicated to the QAM receiver by means of a carrier phase and clock phase lock detection circuit (not shown).
After the QAM receiver IC and its interconnection with the tuner have been produced, both the QAM receiver IC, the tuner and the interconnection of the QAM receiver IC produced are tested. In particular, it is tested whether the tuner T, the anti-aliasing filter AAF and the downstream analog/digital converter ADC are operating correctly. In a measuring circuit of the prior art, this is done with the aid of an external spectrum analyzer for measuring the power density of a frequency spectrum applied.
FIG. 2 shows a measuring arrangement for measuring the tuner of the prior art. A known transmit signal is fed into an input node E preceding the tuner and the signal output by the tuner is applied to the spectrum analyzer at a tapping node A. The spectrum analyzer measures the frequency response of the tuner in order to determine whether it is operating correctly.
FIG. 3 shows a further measuring arrangement of the prior art for measuring the anti-aliasing filter AAF contained in the receiver IC. The AAF filter can be integrated in the receiver IC or precede the latter. In the measuring arrangement shown in FIG. 3, the tapping point A is located within the QAM receiver IC produced so that the tapping after the anti-aliasing filter AAF can only be managed with a very large amount of effort.
FIG. 4 shows a further measuring arrangement for measuring the analog/digital converter within the QAM receiver IC. In the measuring arrangement shown in FIG. 4, both the feed point E and the tapping point A are located inside the receiver IC so that both the signal injection and the signal extraction can only be managed with a very large amount of effort.
The measuring arrangements of the prior art as shown in FIGS. 2 to 4 need an external spectrum analyzer for measuring the components contained in the QAM receiver. Such a spectrum analyzer is very expensive and, moreover, not always available. The configuration of the measuring arrangements shown in FIGS. 2 to 4 is often very elaborate, particularly since the signal feed points E and the tapping points A are partly inside the QAM receiver IC. The signal injection and the signal extraction are additionally made more difficult because of the high signal frequencies.